Gen6 PCIe/CXL 2x8 to 2x8 Retimer
Product Description
PCI6-AD-2xMCIO-2xMCIO-RT — PCIe/CXL Gen6 Retimer Card
The Serial Cables PCI6-AD-2xMCIO-2xMCIO-RT is a PCIe/CXL Gen6 active retimer card designed to extend signal reach in high-speed interconnect validation and deployment environments. Featuring four MCIO SFF-TA-1016 connectors in a compact 76 × 140 × 24mm form factor, the card provides two x8 root-side and two x8 endpoint-side ports, supporting full x16 link configurations as well as bifurcated x8, x4, and x2 lane groupings.
Available with either the Marvell Alaska P, Credo Toucan or Broadcom Vantage 16-lane Gen6 retimer IC, the card supports PCIe Gen1 through Gen6 (64 GT/s) and CXL 3.1, extending channel reach beyond 36 dB at full line rate. The integrated active fan-sink provides thermal management for continuous operation with no software or driver installation required.
Powered via a standard 12V DC jack, the card exposes an SMBus interface header (J1) for optional retimer IC and EEPROM access, making it well-suited for signal integrity validation, cable reach characterization, and system bring-up testing.
Key Specs:
- Retimer IC: Credo Toucan or Marvell Alaska P (16-lane Gen6) or Broadcom (16-lane Gen6)
- Connectors: 4× MCIO x8 (2× Root / 2× Endpoint)
- Protocols: PCIe Gen1–Gen6, CXL 3.1
- Power: 12V DC, max ~10W
- Dimensions: 76 × 140 × 24mm
- No driver/software required
Retimer IC — Marvell Alaska® P (MV-CHP10160)
The MV-CHP10160 exceeds PCI-SIG electrical specifications, supporting greater than 32 dB insertion loss at 64 GT/s (PCIe 6) and greater than 36 dB insertion loss at 32 GT/s (PCIe 5) at 16 GHz Nyquist frequency. Advanced equalization features accommodate various channel topologies, and the device achieves a First Bit Error Rate (FBER) better than 1E−6.
The retimer follows the Intel PCIe 6.0 Retimer Supplemental Footprint for generation-to-generation design compatibility. It is manufactured on an advanced process node and delivers significant power efficiency. Device configuration is supported through SMBus/I³C, EEPROM, or SPI Flash. Integrated diagnostics include on-chip voltage and thermal sensors, an embedded logic analyzer with history FIFO, GPIO status indicators, and IEEE 1149.6 AC-JTAG boundary scan.
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Feature |
Detail |
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Standards & Compatibility |
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PCIe Compliance |
PCI Express Gen 6.x / 5 / 4 / 3 / 2 / 1 |
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CXL Compliance |
CXL 3.x / 2.0 / 1.1 (low-latency cache-coherent mode) |
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Data Rates |
64 GT/s, 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s |
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Encoding |
PAM4 (Gen6/5) and NRZ (Gen4 and below) |
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Lane Count |
32 bi-directional (16 upstream + 16 downstream) |
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Link Bifurcation |
1×16, 2×8, 4×4, 8×2, and additional combinations |
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Hot Plug |
PCIe hot-add and hot-removal per link/partition |
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Footprint Compatibility |
Intel PCIe 6.0 Retimer Supplemental Footprint |
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I/O Performance |
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Insertion Loss (PCIe 6) |
> 32 dB at 64 GT/s (16 GHz Nyquist) |
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Insertion Loss (PCIe 5) |
> 36 dB at 32 GT/s (16 GHz Nyquist) |
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FBER |
Better than 1E−6 |
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Equalization |
Advanced CTLE + DFE + TX FIR; multi-topology support |
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Clocking |
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Clock Input |
PCIe base-spec compliant 100 MHz reference clock |
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Clock Output |
HCSL reference clock output to downstream devices |
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Clocking Modes |
Common Clock, SRIS, and SRNS |
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Management, Debug & Diagnostics |
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Management Interface |
I²C / SMBus with I³C extensions |
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Configuration |
SMBus/I³C, EEPROM, or SPI Flash |
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Sensors |
On-chip voltage and thermal monitoring |
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Diagnostics |
Embedded logic analyzer, history FIFO, advanced telemetry |
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GPIO |
Link status and functional status indication |
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Boundary Scan |
IEEE 1149.6 AC-JTAG |
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Package |
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IC Package |
8.9 mm × 22.8 mm HFETBGA, 0.5 mm minimum ball pitch |
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Power Rails |
Three external power rails |
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DC-Blocking Caps |
Package options for integrated DC-blocking capacitors |
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Simulation Support |
IBIS-AMI model available |
