Gen6 PCIe/CXL Broadcom-based Retimer
Product Description
Gen6 PCIe/CXL Broadcom-based Retimer
Gen6 Retimers are more sophisticated and complex devices than redrivers, designed to overcome some of the inherent downsides of redrivers since the release of PCIe Gen4. They are protocol-aware and are able to recover lost signal data and retransmit a fresh copy of it. They can also eliminate deterministic jitter caused by things like mismatched impedance or crosstalk and reset random jitter.
The Serial Cables Gen6 PCIe/CXL Broadcom-based Retimer is a 16-lane, low-power, low-latency, symmetrical Gen6 PCIe and CXL 3.1 integrated MAC and PHY retimer. This adapter extends the reach between a root complex (RC) and endpoint (EP) by >36 dB of loss on both the sides at 64 GT/s. Each lane is capable of multiple data rates, including Gen6 (64G PAM4) , Gen5 (32G), Gen4 (16G), Gen3 (8G), Gen2 (4G), and Gen1 (2.5G). The bifurcation mux and MAC support groups of 1x 16 lanes, 4x 4 lanes, and 8x 2 lanes. To compensate for any link loss, this Serial Cables retimer performs link training to automatically set the optimal TX-FIR settings. The receiver features integrated and dynamic peaking filter, VGA, DFE, and CDR for signal recovery as well as using a low-cost standard PCIe 100-MHz reference clock.
Included is an on-board micro CPU (mCPU) to monitor key metrics like voltage, current and temperature in real time. It also features a rich set of CLI commands for deep configuration options to fit any test scenario you come across in the lab.
- Compatible with PCIe Gen6/ Gen5/Gen4/Gen3/Gen2/Gen1 and Compute Express Link (CXL 3.1) standards
- Operates at 64, 32, 16, 8, 5, and 2.5 GT/s
- Supports parallel lane groupings per transfer:
- Extends reach to >36 dB at 64 GT/sRX integrates multistage linear EQ and adaptive 16-tap DFE; TX uses 4-tap FIR taps
- Receiver is capable of operating at data rates with REFCLK, independent of transmitter
- Provides clock and data recovery (CDR) tolerance of spread inputs up to 6000 ppm relative to the reference clockSupports LT when connected with an LT-capable link partnerProvides an adjustable loss-of-signal (LOS) detector
- Supports low-power modes
- Supports PCIe L0, L1, and L1 substates power modes
- Supports proprietary low-latency (LL) modes:
- Intel proprietary inband LL entry and exit
- Broadcom proprietary inband LL entry and exit
- Common Clock with and without SSC, SRNS, and SRIS clock mechanism
- Receiver lane (eye) margining
- Receiver detect bypass
- Dynamic pseudo port and polarity orientation
- I²C or SPI master for external EEPROM configuration
- Reference clock output
- Secured bootloader of firmware from the ROM
- Line-side and system-side loopbacks
- PRBS generator and checker
- Single low-cost reference clock input
- JTAG and embedded logic analyzer
- Interoperability with the Broadcom PCIe switches series switch/storage silicon
- Low-power 5-nm CMOS design
- Integrated AC-coupling on high-speed lanes
| User's Manual | Download |
